Tri-level DRAM sense amplifer

ABSTRACT

A sensing system can read from a memory cell configured to store a data bit and to produce a differential signal indicating a data state of the memory cell. The data state can be selected from three data states. An example of the system can include a pair of bit lines, a pair of sense amplifiers (SAs), and a data output circuit. The bit lines are coupled to the memory cell to receive the differential signal. The SAs are each independently coupled to the bit lines through an isolation circuit. The data output circuit can receive outputs from the SAs and indicate the data state of the memory cell based on the outputs.

PRIORITY APPLICATION

This application claims the benefit of priority to U.S. ProvisionalApplication Ser. No. 62/490,904, filed Apr. 27, 2017, which isincorporated herein by reference in its entirety.

BACKGROUND

A memory device, such as a dynamic random access memory (DRAM) device,can include memory cells each configured to store a binary data bit (1or 0) and produce a signal on a bit line that represents the data bit.To read the data bit from a memory cell, a sense amplifier can be usedto amplify the signal on the bit line to a level allowing for reliabledetection of the data bit as “1” (logic high) or “0” (logic low). Somememory devices can store data bits having more than two logic levels.For example, a 3-level DRAM may store data bits having logic levelscorresponding to Vcc (DRAM supply voltage), Vcc/2, and 0. This allowseach data bit to have a third state in addition to the logic high andlow states.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate generally, by way of example, but not by way oflimitation, various embodiments discussed in the present document.

FIG. 1 illustrates an embodiment of a system for tri-level sensing of adynamic random access memory (DRAM) cell.

FIG. 2 illustrates an embodiment of an isolation circuit of the systemof FIG. 1.

FIG. 3 illustrates an embodiment of the DRAM cell of FIG. 1.

FIG. 4 illustrates another embodiment of the DRAM cell of FIG. 1.

FIG. 5 illustrates an embodiment of gut node biasing of the senseamplifiers of FIG. 1.

FIG. 6 illustrates an embodiment of a sense amplifier circuit for use inthe system of FIG. 1.

FIG. 7 illustrates an embodiment of portions of a DRAM device.

FIG. 8 illustrates an embodiment of a method for reading from a DRAMcell.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that the embodiments may be combined, or that otherembodiments may be utilized and that structural, logical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. References to “an”, “one”, or “various” embodimentsin this disclosure are not necessarily to the same embodiment, and suchreferences contemplate more than one embodiment. The following detaileddescription provides examples, and the scope of the present invention isdefined by the appended claims and their legal equivalents.

This document discusses, among other things, a system and method fortri-level sensing in a dynamic random access memory (DRAM) that includescomplementary digit lines with differential signals representing storeddata bits. The DRAM can include an array of memory cells each configuredfor storing a data bit using a 2-transistor, 1-capacitor (“2T-1C”) or2-transistor, 2-capacitor (“2T-2C”) architecture. The capacitor(s) ofeach memory cell charge a complementary pair of digit lines to produce adifferential signal indicating a data state of the memory cell. Possibledata states can include a high state (binary data “1”), a low state(binary data “0”), and a neutral state (lack of data). The neutral statecan be stored in the memory cells by, for example, writing Vcc/2 intothem. The present system provides for reading of such a neutral state,in additional to the binary 1's and 0's, from the memory cells. Invarious embodiments, a third data state can allow for operations notfeasible with two logic states. For example, availability of the thirddata state can enable new types of processor-in-memory (PIM) functions.In another example, two tri-level memory bits can effectively becombined in order to represent 3 binary bits of data, thus creating amulti-level DRAM. In another example, the third data state can also beuseful for error-correcting code (ECC) operations.

The present system uses two sense amplifiers to sense three data statesfrom each memory cell. Both sense amplifiers are connected to the samedigital lines carrying the differential signal from a memory cell, andare enabled for sensing at the same time. Isolation (“ISO”) devices areused to independently feed the differential signal into each senseamplifier without affecting the operation of the other sense amplifier.One sense amplifier is preconditioned to read its gut node digit as “1”(high state), while the other sense amplifier is preconditioned to readits gut digit as “0” (low state). If the memory cell had a “1” or a “0”stored in it, then the differential signal is strong enough to overcomethe built in bias of the sense amplifiers such that both senseamplifiers correctly read these data states. However, if the neutraldata state is stored in the memory cell, the data state is sensed by onesense amplifier senses as a “1” while being sensed by the other senseamplifier as a “0”. The sensing results from both sense amplifiers arethen subjected to an exclusive OR (XOR) operation. If the XOR operationresults in a “0” (i.e., the output of both sense amplifiers are equal),then the sensed results of either sense amplifier can be directly usedas the sensed data state. If the XOR operation results in a “1” (i.e.,the outputs of both sense amplifiers are complementary), then theneutral state is sensed. In various embodiments, the array of memorycells is built using a technology that allows the sense amplifiers andother required circuitry to be placed under the memory cells in ordernot to affect die size substantially.

In various embodiments, the pair of sense amplifiers for sensing eachmemory cell is biased to make them sense certain data states whenpresented with the neutral state signal level. This is accomplished byutilizing the built in gate-to-source/drain overlap capacitance of theISO devices to separate the sense amplifier gut nodes by a predeterminedamount of voltage. When no signal is present (the neutral state), thiscauses the sense amplifiers to flip in the desired direction to resultin either “1” or “0”. When the memory cell state is a “1” or “0”, thelarge signal produced on the gut node of each sense amplifiers overcomesthe built-in bias of that sense amplifier, and both sense amplifiersread the data state correctly.

FIG. 1 illustrates an embodiment of a system 100 for tri-level sensingof a DRAM cell. System 100 can be implemented as a portion of a circuitof a DRAM device. In the illustrated embodiment, system 100 can includea memory cell 102, a pair of complementary bit lines BL-T (bitline-true) and BL-C (bit line-complement), an isolation circuit 104, anda sensing circuit 106.

Memory cell 102 can store a data bit and produce a differential signalacross the pair of complementary bit lines BL-T and BL-C. Thedifferential signal indicates a data state of memory cell 102. The datastate can be selected from three predetermined data states including,for example: a high state (data “1”), a low state (data “0”), and aneutral state (lack of data). Examples of a circuit for memory cell 102are discussed below with reference to FIGS. 3 and 4.

Sensing circuit 106 is coupled to memory cell 102 through isolationcircuit 104 to read the data bit stored in memory cell 102. Sensingcircuit 106 includes a pair of sense amplifiers (SAs) each independentlycoupled to the pair of BL-T and BL-C through isolation circuit 104. Thepair of SAs includes a first SA 108-1 and a second SA 108-2. SA 108-1has a first input (gut node-true) GUT-1T coupled to BL-T throughisolation circuit 104, a second input (gut node-complement) GUT-1Ccoupled to BL-C through isolation circuit 104, and an output configuredto indicate data state being what SA 108-1 reads. SA 108-2 has a firstinput (gut node-true) GUT-2T coupled to BL-T through isolation circuit104, a second input (gut node-complement) GUT-2C coupled to BL-C throughisolation circuit 104, and an output configured to indicate data statebeing what SA 108-2 reads. In various embodiments, SA 1084 and SA 108-2are substantially identical (which means, for example, the two SAs areidentical by design, but with manufacturing tolerances).

Isolation circuit 104 feeds the differential signals to SA 108-1 and SA108-2 independently (without affecting operation of the other). Invarious embodiments, isolation circuit 104 can precondition one of SA108-1 and SA 108-2 to read “1” and the other of SA 1084 and SA 108-2 toread “0”. An example of isolation circuit 104 is discussed below withreference to FIG. 2.

Sensing circuit 106 can include a data output circuit 110 to receiveoutputs from SA 108-1 and SA 108-2 and indicate the data state of memorycell 102 based on the received outputs. In various embodiments, dataoutput circuit 110 indicates a data state equal to the data state readby both SA 108-1 and SA 108-2 when the data states read by SA 1084 andSA 108-2 are equal, and includes the neutral data state when the datastates read by SA 108-1 and SA 108-2 are different. In one embodiment,the outputs from SA 108-1 and SA 108-2 are exclusive-OR (XOR) gated indata output circuit 110 to determine whether the data state of memorycell 102 is the data state read by both SA 108-1 and SA 108-2 or theneutral state. If SA 108-1 reads “0” and SA 108-2 reads “0”, the XORresult is “0”, and the data state of memory cell 102 is “0”. If SA 108-1reads “0” and SA 108-2 reads “1”, the XOR result is “1”, and the datastate of memory cell 102 is neutral. If SA 108-1 reads “1” and SA 108-2reads “0”, the XOR result is “1”, and the data state of memory cell 102is neutral. If SA 108-1 reads “1” and SA 108-2 reads “1”, the XOR resultis “0”, and the data state of memory cell 102 is “1”.

FIG. 2 illustrates an embodiment of an isolation circuit 204, whichrepresents an example of isolation circuit 104. Isolation circuit 204can include a first P-channel isolation (P-ISO) device 212-1A coupledbetween BL-T and GUT-1T (true input of SA 108-1), a first N-channelisolation (N-ISO) device 212-1B coupled between BL-C and GUT-1C(complementary input of SA 108-1), a second N-channel isolation (N-ISO)device 212-2A coupled between BL-T and GUT-2T (true input of SA 108-2),and a second P-channel isolation (P-ISO) device 212-2B coupled betweenBL-C and GUT-2C (complementary input of SA 108-2). These ISO devicesisolate the digit line gut nodes of the sense amplifiers from the digitlines (bit lines). In various embodiments, N-ISO devices 212-1B and212-2A can each include an N-channel metal-oxide semiconductorfield-effect transistor (MOSFET) with an elevated gate voltage. P-ISOdevices 212-1A and 212-2B can each include a P-channel MOSFET with anelevated gate voltage. The elevated gate voltages bias SA 108-1 and SA108-2 to read complementary logic levels during preconditioning beforesensing the data state from memory cell 102.

FIGS. 3 and 4 illustrates examples of memory cell 102. A DRAM cell canbe composed of one transistor and one capacitor (referred to as “1T-1C”,not shown in the figures). One side of the capacitor connects to thetransistor, while the other side of the capacitor connects to areference voltage (e.g., VC2, or Vcc/2, one half of the supply voltageof the DRAM device). The capacitor stores one data state (“1” or “0”)for one memory cell unit. The capacitor discharges to a bit line. Asense amplifier amplifies the differential signal between the bit lineand the reference voltage to sense the data state. System 100 can beimplemented with a DRAM cell that is composed of two transistors and twocapacitors (referred to as “2T-2C”) or a DRAM cell that is composed oftwo transistors and one capacitor (referred to as “2T-1C”), as discussedwith references to FIGS. 3 and 4.

FIG. 3 illustrates an embodiment of a memory cell 302, which representsan example of memory cell 102. Memory cell 302 is a 2T-2C DRAM cellincluding transistors 320 and 322 with gates connected to a word line(WL) for enabling data state sensing and capacitors 321 and 323. Oneside of each of capacitors 321 and 323 connects to transistors 320 and322, respectively, while the other side of each of capacitors 321 and323 connects to a fixed voltage (e.g., VC2). Capacitors 321 and 323store complementary data for one memory cell unit (e.g., capacitor 321stores true data, and capacitor 323 stores complementary data).Capacitor 321 discharges to BL-T, and capacitor 323 discharges to BL-C.Sensing circuit 106 amplifies the differential signal between BL-T andBL-C to sense the data state stored in memory cell 302. No otherreference voltage is required for the sensing. This 2T-2C memory cellcan provide a differential signal that has an amplitude twice as largeas the differential signal produced by the 1T-1C memory cell.

FIG. 4 illustrates another embodiment of a memory cell 402, whichrepresents another example of memory cell 102. Memory cell 402 is a2T-1C DRAM cell including transistors 424 and 426 with gates connectedto a word line (WL) for enabling data state sensing and a capacitor 425.Each plate of capacitor 425 connects to one of transistors 424 and 426(with no plate connected to a fixed voltage). Capacitor 425 dischargesto BL-T and BL-C. Sensing circuit 106 amplifies the differential signalthe differential signal between BL-T and BL-C to sense the data statestored in memory cell 402. No other reference voltage is required forthe sensing. This 2T-1C memory cell can provide a differential signalthat has an amplitude three times as large as the differential signalproduced by the 1T-1C memory cell.

FIG. 5 illustrates an embodiment of gut node biasing of SA 108-1 and SA108-2. The voltage levels at BL-T, BL-C, GUT-1T, GUT-1C, GUT-2T, andGUT-2C are shown for each data state read by SA 108-1 and SA 108-2. Whenword line (WL) is enabled, SA 108-1 and SA 108-2 are preconditioned bybiasing their gut nodes with voltage levels at BL-T and BL-C. When theISO devices 212 are enabled, SA 108-1 and SA 108-2 read the data state.

FIG. 6 illustrates an embodiment of a sense amplifier circuit for use insystem 100. The circuit as shown in FIG. 6 can be used as, for example,SA 108-1 with P-ISO 212-1A and N-ISO 212-1B. With M1 changed to anN-channel MOSFET and M2 changed to a P-channel MOSFET (i.e., devicetypes for M1 and M2 swapped), the circuit can be used as, for example,SA 108-2 with N-ISO 212-2A and P-ISO 212-2B.

Elements and nodes of the circuit are as follows:

-   -   RNL: The voltage applied to the N-sense amplifier (M5-M6) to        enable/disable them.    -   ACT: The voltage applied to the P-sense amplifier (M7-M8) to        enable/disable them.    -   ISOa: The gate of the isolation device connected to array digit        “a”.    -   ISOb: The gate of the isolation device connected to array digit        “b”.    -   VC2: One half of the supply voltage, also referred to as Vcc/2,        AVC2, or DVC2.    -   Eq: The signal that controls the devices in the sense amplifier        that equilibrate the digits back to VC2.    -   Da: A digit line of the sense amplifier, to be considered to        come from the adjacent memory array that is activated, so it is        the digit that is being used for reading and writing.    -   Db: A digit line of the sense amplifier, to be considered to        come from the adjacent memory array that is not activated, so it        is the digit that is being used as a reference for sensing.    -   IOa: The input/output line for writing to and reading from the        sense amplifier, connected to digit a.    -   IOb: The input/output line for writing to and reading from the        sense amplifier, connected to digit b.    -   CS: The Column Select enable signal, which controls whether the        inputs/outputs are connected to the digits or not.    -   GUTA, GUTB: SA gut nodes.    -   VCCP!: An elevated voltage applied to the gate of an N-channel        device which allows it to pass the full Vcc level though it, the        gate voltage of the access device transistors in the memory        array.

VBBSA!: The bulk voltage for the N-channel devices located in the senseamplifier, usually around −0.3V, allowing for tuning the thresholdvoltage of the N-sense amplifiers.

-   -   M1, M2: MOSFETs used as isolation devices.    -   M3-M10: MOSFETs used as sense amplifiers.    -   C1, C2: SA gut node parasitic capacitors.    -   C3, C4: Showing built-in gate to source/drain capacitances used        to couple the SA gut nodes.

FIG. 7 illustrates an embodiment of portions of a DRAM device thatinclude an array of 2T-1C cells. A pair of SA1 and SA2 is used to readthe data state from each of the cells.

FIG. 8 illustrates an embodiment of a method 830 for reading from amemory cell such as a DRAM cell. In one embodiment, method 830 can beperformed by system 100.

At 831, a differential signal is produced across a pair of complementarybit lines, such as a pair of a true bit line (BL-T) and a complementarybit line (BL-C). The differential signal indicates the data state. Inone embodiment, the data state can be one of a high state (“1”), a lowstate (“0”), and a neutral state (e.g., indication of lacking of data,created by writing into the memory cell a voltage level beingapproximately one half of a supply voltage for the DRAM device. In oneembodiment, the memory cell has a 2T-1C structure, and the differentialsignal is produced by discharging a capacitor of the memory cell to thepair of complementary bit lines. In another embodiment, the memory cellhas a 2T-2C structure, and the differential signal is produced bydischarging a first capacitor of the memory cell to a first bit line ofthe pair of complementary bit lines and discharging a second capacitorof the memory cell to a second bit line of the pair of complementary bitlines.

At 832, the differential signal is fed independently to each senseamplifier (SA) of a pair of first SA (SA1) and second SA (SA2) throughan isolation circuit coupled between the pair of complementary bit linesand the pair of SA1 and SA2. In one embodiment, the differential signalis fed to the SA1 using (1) a first P-channel isolation (P-ISO) devicecoupled between the BL-T and a first input of the SA1 and (2) a firstN-channel isolation (N-ISO) device coupled between the BL-C and a secondinput of the SA1. The differential signal is also fed to the SA2 using(1) a second P-channel isolation (P-ISO) device coupled between the BL-Cand the second input of the SA2 and (2) a second N-channel isolation(N-ISO) device coupled between the BL-T and the first input of the SA2.

At 833, the pair of SA1 and SA2 are preconditioned such that SM and SA2produce outputs indicating complementary logic levels. For example, SA1and SA2 are biased such that SA1 reads “1” and SA2 reads “0”.

At 834, the data state of the memory cell is sensed using thepreconditioned SA1 and SA2. At 835, the data state is determined basedon the outputs of SA1 and SA2. The data state is indicated to be equalto the data state as sensed by SA1 and the data state as sensed by SA2when the data state as sensed by SA1 and the data state as sensed by SA2are equal. The data state is indicated to be the neutral data state whenthe data state as sensed by SA1 and the data state as sensed by SA2 arenot equal. In one embodiments, the outputs of SA1 and SA2 to anexclusive OR gate to determine whether the data state as sensed by SA1and the data state as sensed by SA2 are equal. If SA1 reads “0” and SA2reads “0”, the data state is “0”. If SA1 reads “0” and SA2 reads “1”,the data state is neutral. If SA1 reads “1” and SA2 reads “0”, the datastate is neutral. If SA1 reads “1” and SA2 reads “1”, the data state is‘1”.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples”. Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples one or more aspects thereof) shown or described herein.

It will be understood that when an element is referred to as being “on,”“connected to” or “coupled with” another element, it can be directly on,connected, or coupled with the other element or intervening elements maybe present. In contrast, when an element is referred to as being“directly on,” “directly connected to” or “directly coupled with”another element, there are no intervening elements or layers present. Iftwo elements are shown in the drawings with a line connecting them, thetwo elements can be either be coupled, or directly coupled, unlessotherwise indicated.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment, and it is contemplated that such embodiments can be combinedwith each other in various combinations or permutations. The scope ofthe invention should be determined with reference to the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

What is claimed is:
 1. A sensing system for reading from a memory cellconfigured to store a data bit and to produce a differential signalindicating a data state of the memory cell, the data state selected fromthree data states, the system comprising: a pair of bit lines coupled tothe memory cell to receive the differential signal; a pair of senseamplifiers (SAs); an isolation circuit coupled between the pair of bitlines and the pair of SAs to independently couple each SA of the pair ofSAs to the pair of bit lines; and a data output circuit configured toreceive outputs from the pair of SAs and indicate the data state of thememory cell based on the outputs.
 2. The system of claim 1, wherein thedata output circuit is configured to indicate the data state as one of ahigh state indicating data “1”, a low state indicating data “0”, and aneutral state indicating lacking of data.
 3. The system of claim 2,wherein the isolation circuit is configured to precondition one of thepair of SAs to read data “1” and the other of the pair of SAs to readdata “0”.
 4. The system of claim 3, wherein the pair of bit linescomprises a true bit line (BL-T) and a complementary bit line (BL-C),and the pair of SAs comprises: a first sense amplifier (SA1) having anSA1 input A coupled to the BL-T, an SA1 input B coupled to the BL-C, andan SA1 output configured to indicate an SA1 data state; and a secondsense amplifier (SA2) having an SA2 input A coupled to the BL-T, an SA2input B coupled to the BL-C, and an SA2 output configured to indicate anSA2 data state.
 5. The system of claim 4, wherein the SA1 and the SA2are substantially identical.
 6. The system of claim 4, wherein theisolation circuit comprises a first P-channel isolation (P-ISO) devicecoupled between the BL-T and the SA1 input A; a first N-channelisolation (N-ISO) device coupled between the BL-C and the SA1 input B; asecond P-channel isolation (P-ISO) device coupled between the BL-C andthe SA2 input B; and a second N-channel isolation (N-ISO) device coupledbetween the BL-T and the SA2 input A.
 7. The system of claim 4, whereinthe data output circuit is configured to indicate the data state to beequal to the SA1 data state and the SA2 data state when the SA1 datastate and the SA2 data state are equal, and to indicate the data stateto be the neutral data state when the SA1 data state and the SA2 datastate are not equal.
 8. The system of claim 7, further comprising anexclusive OR (XOR) gate having a first XOR input coupled to the SA1output, a second XOR input coupled to the SA2 output, and an XOR outputindicating whether the SA1 data state and the SA2 data state are equal.9. A memory device, comprising: a pair of bit lines; a memory cellconfigured to store a data bit and produce a differential signal acrossthe pair of bit lines, the differential signal indicating a data stateof the memory cell, the data state selected from a high state, a lowstate, and a neutral state; a pair of sense amplifiers (SAs); anisolation circuit coupled between the pair of bit lines and the pair ofSAs, the isolation circuit configured to feed the differential signal toeach SA of the pair of SAs independently; and a data output circuitconfigured to receive outputs from the pair of SAs and indicate the datastate of the memory cell based on the outputs.
 10. The device of claim9, wherein the memory cell comprises two transistors and two capacitors.11. The device of claim 9, wherein the memory cell comprises twotransistors and one capacitor.
 12. The device of claim 9, wherein theisolation circuit is configured to precondition an SA of the pair of SAsto read data “1” and the other SA of the pair of SAs to read data “0”.13. The device of claim 12, wherein the pair of SAs comprises a firstoutput indicating the data state as sensed by one SA of the pair of SAsand a second output indicating the data state as sensed by the other SAof the pair of SAs, and data output circuit is configured to indicatethe data state to be the data state indicated by both the first outputand the second output when the first output and the second outputindicate the same data state, and to indicate the data state to be theneutral state when the first output and the second output indicatedifferent data states.
 14. A method for sensing a data state from amemory cell of a memory device, the method comprising: producing adifferential signal across a pair of bit lines, the differential signalindicating the data state as one of a high state, a low state, and aneutral state; feeding the differential signal independently to eachsense amplifier (SA) of a pair of first SA (SA1) and second SA (SA2)through an isolation circuit coupled between the pair of bit lines andthe pair of SA1 and SA2; preconditioning the pair of SA1 and SA2 suchthat SA1 and SA2 produce outputs indicating complementary logic levels;sensing the data state using the preconditioned pair of SA1 and SA2; anddetermining the data state based on the outputs of SA1 and SA2.
 15. Themethod of claim 14, wherein producing the differential signal comprisesdischarging a capacitor of the memory cell to the pair of bit lines. 16.The method of claim 14, wherein producing the differential signalcomprises discharging a first capacitor of the memory cell to a firstbit line of the pair of bit lines and discharging a second capacitor ofthe memory cell to a second hit line of the pair of hit lines.
 17. Themethod of claim 14, wherein producing the differential signal across apair of bit lines comprises producing the differential signal across apair of a true bit line (BL-T) and a complementary bit line (BL-C), andfeeding the different signal independently to each SA of the pair of SA1and SA2 using the isolation circuit comprises: feeding the differentialsignal to SA1 using a first P-channel isolation (P-ISO) device coupledbetween the BL-T and a first input of SA1 and a first N-channelisolation (N-ISO) device coupled between the BL-C and a second input ofSA1; and feeding the differential signal to SA2 using a second P-channelisolation (P-ISO) device coupled between the BL-C and the second inputof SA2 and a second N-channel isolation (N-ISO) device coupled betweenthe BL-T and the first input of SA2.
 18. The method of claim 17, whereindetermining the data state comprises: indicating a data state equal tothe data state as sensed by SA1 and the data state as sensed by SA2 whenthe data state as sensed by SA1 and the data state as sensed by SA2 areequal; and indicating the neutral data state when the data state assensed by SA1 and the data state as sensed by SA2 are not equal.
 19. Themethod of claim 18, wherein determining the data state comprises feedingthe outputs of SA1 and SA2 to an exclusive OR gate to determine whetherthe data state as sensed by SA1 and the data state as sensed by SA2 areequal.
 20. The method of claim 19, comprising creating the neutral stateby writing into the memory cell a voltage level being approximately onehalf of a supply voltage for the DRAM device.